High speed caching coherence method and smp system

Embodiments of the invention address deficiencies of the art in respect to cache coherency management and provide a novel and non-obvious method, system and apparatus for silent invalid state transition handling in an SMP environment. In one embodiment of the invention, a cache coherency method can...

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Bibliographic Details
Main Authors VANDERPOOL BRIAN T, PHAM NGAN N, KORNEGAY MARCUS L
Format Patent
LanguageChinese
English
Published 24.08.2011
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Embodiments of the invention address deficiencies of the art in respect to cache coherency management and provide a novel and non-obvious method, system and apparatus for silent invalid state transition handling in an SMP environment. In one embodiment of the invention, a cache coherency method can be provided. The cache coherency method can include identifying an invalid state transition for a cache line in a local node, evicting a corresponding cache directory entry for the cache line, forwarding an invalid state transition notification to a node controller for a home node for the cache line in order for the home node to evict a corresponding cache directory entry for the cache line, and relinquishing ownership of the cache line to the home node.
Bibliography:Application Number: CN20071112011