DIGITAL PHASE SHIFTER

• Main Authors: LOGUE, JOHN D, CHING, ALVIN Y, PERCEY, ANDREW K, GOETTING, F. ERICH, YOUNG, STEVEN P
• Format: Patent
• Language: English; French
• Published: 14.12.2010
• Subjects: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES; BASIC ELECTRONIC CIRCUITRY; CALCULATING; COMPUTING; COUNTING; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRIC DIGITAL DATA PROCESSING; ELECTRICITY; PHYSICS; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

After a delay lock loop (300) synchronizes a reference clock signal with a skewed clock signal (REF-CLK), a digital phase shifter (350) can be used to shift the skewed clock signal (S-CLK) by a small amount with respect to the reference clock signal. The tap/trim settings of a delay line (310) in the main path of the delay lock loop can be transmitted to the digital phase shifter, thereby informing the digital phase shifter of the period of the reference clock signal. In response, the digital phase shifter provides a phase control signal that introduces a delay to either the reference clock signal or the skew clock signal. The phase control signal is proportional to a predetermined fraction of the period of the reference clock signal.