SCHALTUNGSANORDNUNG ZUR STÖRBEFREIUNG EINES PULSRAHMENSIGNALS

The circuit uses a counter (Ct) indexed by the trailing flank of each clock pulse (CLK) and providing an output signal upon reaching a given count, corresponding to a given number of clock pulses. The input pulse frame signal (FSi) is fed to a delay element (VZ), providing a counter resetting signal...

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Bibliographic Details
Main Authors LEITOL, STEFAN, PREY, GERHARD, GRAD
Format Patent
LanguageGerman
Published 15.11.1997
Edition6
Subjects
BASIC ELECTRONIC CIRCUITRY
CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
MULTIPLEX COMMUNICATION
PHYSICS
PULSE TECHNIQUE
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Summary:The circuit uses a counter (Ct) indexed by the trailing flank of each clock pulse (CLK) and providing an output signal upon reaching a given count, corresponding to a given number of clock pulses. The input pulse frame signal (FSi) is fed to a delay element (VZ), providing a counter resetting signal at the end of the pulse frame signal after a delay time corresponding to the noise interval. The leading flanks of the clock signal control a bistable flip-flop (BK), receiving the output from the counter as an input signal and providing the noise-free pulse frame signal (FSo) at its output.
Bibliography:Application Number: AT19950113632T