一种基于位线电荷循环的低功耗SRAM阵列设计
为了降低静态随机存储器(SRAM)的动态功耗,提出一种基于位线电荷循环的读写辅助电路的SRAM阵列.与传统设计性比,辅助电路中转和保存了在读写操作中本该被直接泄放掉的位线电荷,并重新用于下一个周期的位线充电.提出的SRAM存储器采用标准14 nm FinFET spice模型搭建,电源供电电压为0.8 V.仿真结果表明,与传统设计相比,提出的存储阵列的功耗可以降低23％～43％,并将SNM和WNM至少提高25％和647.9％....
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| Published in | 北京大学学报（自然科学版） Vol. 57; no. 5; pp. 815 - 822 |
|---|---|
| Main Authors | , , , |
| Format | Journal Article |
| Language | Chinese |
| Published |
北京大学微电子学研究所, 北京 100871%北京大学微电子器件与电路重点实验室, 北京 100871
20.09.2021
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| Subjects | |
| Online Access | Get full text |
| ISSN | 0479-8023 |
| DOI | 10.13209/j.0479-8023.2021.039 |
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| Abstract | 为了降低静态随机存储器(SRAM)的动态功耗,提出一种基于位线电荷循环的读写辅助电路的SRAM阵列.与传统设计性比,辅助电路中转和保存了在读写操作中本该被直接泄放掉的位线电荷,并重新用于下一个周期的位线充电.提出的SRAM存储器采用标准14 nm FinFET spice模型搭建,电源供电电压为0.8 V.仿真结果表明,与传统设计相比,提出的存储阵列的功耗可以降低23％～43％,并将SNM和WNM至少提高25％和647.9％. |
|---|---|
| AbstractList | 为了降低静态随机存储器(SRAM)的动态功耗,提出一种基于位线电荷循环的读写辅助电路的SRAM阵列.与传统设计性比,辅助电路中转和保存了在读写操作中本该被直接泄放掉的位线电荷,并重新用于下一个周期的位线充电.提出的SRAM存储器采用标准14 nm FinFET spice模型搭建,电源供电电压为0.8 V.仿真结果表明,与传统设计相比,提出的存储阵列的功耗可以降低23％～43％,并将SNM和WNM至少提高25％和647.9％. |
| Author | 贾嵩 张瀚尊 王源 杨建成 |
| AuthorAffiliation | 北京大学微电子学研究所, 北京 100871%北京大学微电子器件与电路重点实验室, 北京 100871 |
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| Author_FL | JIA Song ZHANG Hanzun YANG Jiancheng WANG Yuan |
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| DocumentTitle_FL | A Charge Recycling Scheme with Read and Write Assist for Low Power SRAM Design |
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| Keywords | SRAM;位线电荷循环;读写辅助 |
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| Title | 一种基于位线电荷循环的低功耗SRAM阵列设计 |
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