Graph-Based Code Restructuring Targeting HLS for FPGAs

• Published in: Applied Reconfigurable Computing Vol. 11444; pp. 230 - 244
• Main Authors: Ferreira, Afonso Canas, Cardoso, João M. P.
• Format: Book Chapter
• Language: English
• Published: Switzerland Springer International Publishing AG 2019; Springer International Publishing
• Series: Lecture Notes in Computer Science
• Subjects: FPGA; Graph transformations; Hardware accelerators; HLS; Software code restructuring
• ISBN: 3030172260; 9783030172268
• ISSN: 0302-9743; 1611-3349
• DOI: 10.1007/978-3-030-17227-5_17

High-level synthesis (HLS) is of paramount importance to enable software developers to map critical computations to FPGA-based hardware accelerators. However, in order to generate efficient hardware accelerators one needs to apply significant code transformations and adequately use the directive-driven approach, part of most HLS tools. The code restructuring and directives needed are dependent not only of the characteristics of the input code but also of the HLS tools and target FPGAs. These aspects require a deep knowledge about the subjects involved and tend to exclude software developers. This paper presents our recent approach for automatic code restructuring targeting HLS tools. Our approach uses an unfolded graph representation, which can be generated from program execution traces, and graph-based optimizations, such as folding, to generate suitable HLS C code. In this paper, we describe the approach and the new optimizations proposed. We evaluate the approach with a number of representative kernels and the results show its capability to generating efficient hardware implementations only achievable using manual restructuring of the input software code and manual insertion of adequate HLS directives.