A 32-Bit Binary Floating Point Neuro-Chip

The need for high precision calculations in various scientific disciplines has led to development of systems with various solutions specific to the problem on hand. The complexity of such systems not withstanding, a generic solution could be the use of neural networks. To be able to leverage the bes...

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Published inAdvances in Natural Computation pp. 1015 - 1021
Main Authors Kala, Keerthi Laal, Srinivas, M. B.
Format Book Chapter Conference Proceeding
LanguageEnglish
Published Berlin, Heidelberg Springer Berlin Heidelberg 2005
Springer
SeriesLecture Notes in Computer Science
Subjects
Applied sciences
Artificial intelligence
Computer science; control theory; systems
Exact sciences and technology
Floating point
Floating point arithmetic
Neural network
Computer simulation
Online AccessGet full text
ISBN9783540283201
354028320X
3540283234
9783540283232
ISSN0302-9743
1611-3349
DOI10.1007/11539902_130

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Abstract The need for high precision calculations in various scientific disciplines has led to development of systems with various solutions specific to the problem on hand. The complexity of such systems not withstanding, a generic solution could be the use of neural networks. To be able to leverage the best out of the neural network, hardware implementations are ideal as they give speed-up of several orders of magnitude over software simulations. A simple architecture for such a neuro-chip is proposed in this paper. The neuro-chip supports the current draft version of the IEEE-754 standard for floating-point arithmetic. The synthesis results indicate an estimated 84 MCUPS speed of operation.
AbstractList The need for high precision calculations in various scientific disciplines has led to development of systems with various solutions specific to the problem on hand. The complexity of such systems not withstanding, a generic solution could be the use of neural networks. To be able to leverage the best out of the neural network, hardware implementations are ideal as they give speed-up of several orders of magnitude over software simulations. A simple architecture for such a neuro-chip is proposed in this paper. The neuro-chip supports the current draft version of the IEEE-754 standard for floating-point arithmetic. The synthesis results indicate an estimated 84 MCUPS speed of operation.
Author Kala, Keerthi Laal
Srinivas, M. B.
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Ong, Yew Soon
Chen, Ke
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Keywords Floating point
Floating point arithmetic
Neural network
Computer simulation
Language English
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Snippet The need for high precision calculations in various scientific disciplines has led to development of systems with various solutions specific to the problem on...
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SubjectTerms Applied sciences
Artificial intelligence
Computer science; control theory; systems
Exact sciences and technology
Title A 32-Bit Binary Floating Point Neuro-Chip
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