A 1-MHZ bandwidth 3.6-GHz 0.18-μm CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise

• Published in: IEEE journal of solid-state circuits Vol. 41; no. 4; pp. 966 - 980
• Main Authors: MENINGER, Scott E, PERROTT, Michael H
• Format: Conference Proceeding Journal Article
• Language: English
• Published: New York, NY Institute of Electrical and Electronics Engineers 01.04.2006
• Subjects: Applied sciences; Bandwidth; Circuit properties; Circuits; Circuits of signal characteristics conditioning (including delay circuits); Design. Technologies. Operation analysis. Testing; Detectors; Dividers; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Integrated circuits; Noise; Oscillators, resonators, synthetizers; Phase error; Quantization; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal convertors; Synthesizers; Wide band noise; Phase noise; Second order; Prototype; noise cancellation; Noise reduction; Microwave transmitter; Frequency synthesizer; Sigma-delta modulation; AD converter; frequency synthesis; Complementary MOS technology; Minimum shift keying; Root mean square value; Active circuit; Fractional-N; Closed loop; Arithmetic circuit; Low noise circuit; DA converter; Mismatching; Phase locked loop; Quantization noise; Phase detector; Integrated circuit; Divider
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2006.870894

A frequency synthesizer architecture capable of simultaneously achieving high closed-loop bandwidth and low output phase noise is presented. The proposed topology uses a mismatch compensated, hybrid phase/frequency detector and digital-to-analog converter (PFD/DAC) circuit to perform active cancellation of fractional-N quantization noise. When compared to a classical second-order capital sigma Delta synthesizer, the prototype PFD/DAC synthesizer demonstrates >29 dB quantization noise suppression, without calibration, resulting in a fractional-N synthesizer with 1-MHz closed-loop bandwidth and -155 dBc/Hz phase noise at 20-MHz offset for a 3.6-GHz output. An on-chip band select divider allows the synthesizer to be configured as a dual-band (900 MHz/1.8 GHz) direct modulated transmitter capable of transmitting 271-kb/s GMSK data with less than 3 degrees of rms phase error.