Charge sharing write driver and half‐VDD pre‐charge 8T SRAM with virtual ground for low‐power write and read operation

• Published in: IET circuits, devices & systems Vol. 12; no. 1; pp. 94 - 98
• Main Authors: Maroof, Naeem, Kong, Bai‐Sun
• Format: Journal Article
• Language: English
• Published: Stevenage The Institution of Engineering and Technology 01.01.2018; John Wiley & Sons, Inc
• Subjects: 8T design; BL CSWD; C6T design; C8T design; charge sharing; Charging; conventional 6T design; conventional 8T design; driver circuits; dynamic read power; Energy dissipation; Leakage current; leakage current compensation block; low-power electronics; low-power read operation; low-power write-read operation; pre-charge 8T SRAM; rail-to-rail levels; RBL leakages; RBL pre-charge scheme; read BL pre-charge scheme; single-ended 8T SRAM; SRAM chips; Static random access memory; supply voltage; Transistors; virtual ground; virtual ground rail; WE signal assertion; write bitline charge sharing write driver; write BL pair; write dynamic power dissipation; write enable signal assertion; write power dissipation
• ISSN: 1751-8598; 1751-858X; 1751-8598
• DOI: 10.1049/iet-cds.2017.0146

A novel write bitline (BL) charge sharing write driver (CSWD) and a half‐VDD read BL (RBL) pre‐charge scheme is presented for a single‐ended 8T static random access memory (SRAM). Before write enable (WE) signal assertion, CSWD equalises the write BLs by allowing their charge sharing. Both write BLs are equalised at the middle value of supply voltage using leakage current compensation block. Afterwards, as WE signal is asserted, CSWD produces the rail‐to‐rail levels at write BL pair. Charging of a BL from half‐VDD to VDD essentially reduces the write dynamic power dissipation by 50%. Half‐VDD pre‐charging is used for RBL to achieve low‐power read operation. Read port is powered by virtual ground rail to improve the RBL leakages. The authors compare the proposed 8T design (P8T) with conventional 6T (C6T) and 8T (C8T) designs in a 45 nm technology node. Write power dissipation is reduced by 42% and dynamic read power is reduced by more than 39%. Overall leakages are reduced by more than 18% compared with C6T and Ion/Ioff ratio of the RBL is improved by more than two orders of magnitude compared with conventional 8T (C8T).