Latch and Flip-Flop Design Using Memristors and Transmission Gates with Timer Counter Implementation

• Published in: International Conference on Signal Processing and Communication (Online) pp. 845 - 849
• Main Authors: Rayer, Aditya, Ganesh, Mavulluru, Tanwar, Lavi
• Format: Conference Proceeding
• Language: English
• Published: IEEE 20.02.2025
• Subjects: Flip-Flop; Flip-flops; Latch; Latches; Logic gates; Memristors; MRL; Pass Transistor; Sequential circuits; Signal processing; Switches; Switching circuits; TEAM; Timer Counter; Transistors; Transmission Gate; Voltage
• ISSN: 2643-444X
• DOI: 10.1109/ICSC64553.2025.10967986

Memristors are a combination of the words Memory and Resistor, it never forgets. It is a passive element which remembers the amount of current that flowed through it and is small in size. All these qualities of a memristor make it highly advantageous and useful in the upcoming times for chip manufacturing and designing. Latches are sequential circuits using them in master-slave configuration a flip flop can be generated which is highly useful in applications such as counters, registers, etc. In this paper we implement a Modified version of D-latch and flip flop using memristors and Transmission gates to improve the switching speed and to obtain full voltage swing. Further we show a comparative analysis of proposed modified D-latch and flip-flop with an earlier method along with a timer counter as an application of the D-flip flop circuit. Paper also explains the challenges of using MRL gates in complex circuits. TEAM model of memristor and 180nm technology node files are used in simulation of all the circuits using Cadence Virtuoso.