APA (7th ed.) Citation

Rayer, A., Ganesh, M., & Tanwar, L. (2025, February 20). Latch and Flip-Flop Design Using Memristors and Transmission Gates with Timer Counter Implementation. International Conference on Signal Processing and Communication (Online), 845-849. https://doi.org/10.1109/ICSC64553.2025.10967986

Chicago Style (17th ed.) Citation

Rayer, Aditya, Mavulluru Ganesh, and Lavi Tanwar. "Latch and Flip-Flop Design Using Memristors and Transmission Gates with Timer Counter Implementation." International Conference on Signal Processing and Communication (Online) 20 Feb. 2025: 845-849. https://doi.org/10.1109/ICSC64553.2025.10967986.

MLA (9th ed.) Citation

Rayer, Aditya, et al. "Latch and Flip-Flop Design Using Memristors and Transmission Gates with Timer Counter Implementation." International Conference on Signal Processing and Communication (Online), 20 Feb. 2025, pp. 845-849, https://doi.org/10.1109/ICSC64553.2025.10967986.