A 0.7-V 26.2-28.5 GHz Dual-Loop Double-Sampling PLL with Floating Capacitor OTA Based Gm-CP Achieving a 45.4-fsRMS Jitter

• Published in: Proceedings of the Custom Integrated Circuits Conference pp. 1 - 3
• Main Authors: Chang, Jun, Liang, Hongzhi, Luo, Yixiao, Peng, Zeyu, Li, Zhe, Shen, Yi, Liu, Shubin, Zhu, Zhangming
• Format: Conference Proceeding
• Language: English
• Published: IEEE 13.04.2025
• Subjects: Jitter; Low voltage; Modulation; MOSFET; Passive filters; Phase locked loops; Phase noise; Transceivers; Voltage control; Voltage-controlled oscillators

Complex low-voltage (LV) digitally-assisted calibration and equalization techniques are usually integrated with mixed-signal circuits such as SerDes transceivers and RF-frontend with the potential to significantly develop energy efficiency. To serve this purpose, prior art LV supply phase-locked loo...