A 0.7-V 26.2-28.5 GHz Dual-Loop Double-Sampling PLL with Floating Capacitor OTA Based Gm-CP Achieving a 45.4-fsRMS Jitter - Chang, Jun; Liang, Hongzhi; Luo, Yixiao; Peng, Zeyu; Li, Zhe; Shen, Yi; Liu, Shubin; Zhu, Zhangming (Proceedings of the Custom Integrated Circuits Conference, 2025)
Complex low-voltage (LV) digitally-assisted calibration and equalization techniques are usually integrated with mixed-signal circuits such as SerDes transceivers and RF-frontend with the potential to significantly develop energy efficiency. To serve this purpose, prior art LV supply phase-locked loops (PLLs) have been introduced with the aim of developing power integrity and efficiency [1], [2]. But, the high on-resistance and deteriorating noise parameters of MOS transistors under LV supply pose significant challenges in meeting both noise and high-speed performance requirements, simultaneously. From the perspective of the noise performance, double-sampling (DS) PLLs have shown promising ultra-low jitter features by enabling a significant reduction of in-band noise [3]-[5]. However, the DS phase detector (PD) gain, including a steeply descending GM, needs to balance the phase noise (PN) and loop stability. Dual-loop (DL) PLLs have been extensively used in virtue of their superior flexible bandwidth [6], [7]. Unfortunately, DL PLLs typically rely on the discharge current ratio between the proportional and integral charge pump (CP), suffering from the noise contribution and two forward path mismatches. In addition, the LV CP poses a primary challenge on the charge/discharge current mismatch, deteriorating the reference spur [8]. Since the CP outputs are directly used to control the VCO by a passive filter, the LV supply cannot support the voltage headroom and the channel length modulation in current mirrors, simultaneously.