First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles

• Published in: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) pp. 1 - 2
• Main Authors: Chen, Yu-Rui, Liu, Yi-Chun, Zhao, Zefu, Hsieh, Wan-Hsuan, Lee, Jia-Yang, Tu, Chien-Te, Huang, Bo-Wei, Wang, Jer-Fu, Chueh, Shee-Jier, Xing, Yifan, Chen, Guan-Hua, Chou, Hung-Chun, Woo, Dong Soo, Lee, M. H., Liu, C. W.
• Format: Conference Proceeding
• Language: English
• Published: JSAP 11.06.2023
• Subjects: Computer architecture; Gallium arsenide; Phosphorus; Superlattices; Very large scale integration; Voltage; Zirconium

The large memory window of 1.8\mathrm{~V} at the low write voltage of 2\mathrm{~V} is achieved by stacked two nanosheet (NS) gate-allaround (GAA) Ge 0.98 Si 0.02 FeFETs with the channel phosphorus concentration larger than 1\mathrm{E}18\mathrm{~cm}^{-3}, enabling the erase of GAA FeFET. Isotropic we...