Deep Learning Based Automatic Detection Algorithm of Atrial Fibrillation Implemented on FPGA
Paroxysmal atrial fibrillation (PAF) is one of the most common arrhythmic diseases in clinical practice. The traditional method of PAF diagnosis is achieved by manual analysis of the patient's electrocardiogram by the doctor, which leads to significant manpower consumption and potential misdiag...
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Published in | 2024 IEEE 5th International Conference on Pattern Recognition and Machine Learning (PRML) pp. 330 - 334 |
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Main Authors | , , , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
19.07.2024
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Subjects | |
Online Access | Get full text |
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Summary: | Paroxysmal atrial fibrillation (PAF) is one of the most common arrhythmic diseases in clinical practice. The traditional method of PAF diagnosis is achieved by manual analysis of the patient's electrocardiogram by the doctor, which leads to significant manpower consumption and potential misdiagnosis and missed conditions. To cope with such limitations, this paper proposes an automatic diagnosis algorithm for atrial fibrillation (AF) based on ECG signals using convolution neural networks (CNNs). The algorithm utilized a one-dimensional convolution neural network based on the classical CNN Lenet-5 network structure, to automatically identify the RR interval characteristics of AF. The RR interval sequences were employed from a public database of 23 patients with AF (high-risk group) and 18 healthy subjects (normal group). The ten-fold cross- validation method was used to evaluate the model's performance through three metrics: specialty, sensitivity, and accuracy. Conclusively, the experimental results revealed that the average specialty (Spe), sensitivity (Sen), and accuracy (Acc) for automatic recognition of AF ECG signals achieved 98.61%, 98.72%, and 98.64%. The model was implemented on FPGA with optimization strategies including pipeline architecture and fixed-point number representation instead of floating-point number, resulting in the greatly reduced FPGA hardware resource of the model after optimization on the premise of maintaining accuracy. |
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DOI: | 10.1109/PRML62565.2024.10779948 |