Characterization of on die capacitance and silicon measurement correlation

• Published in: 2015 International Conference on Electronics Packaging and iMAPS All Asia Conference (ICEP-IAAC) pp. 739 - 742
• Main Authors: Li Chuang Quek, Ming Dak Chai, Heng Chuan Shu
• Format: Conference Proceeding
• Language: English
• Published: The Japan Institute of Electronics Packaging 01.04.2015
• Subjects: Capacitance; Correlation; Integrated circuit modeling; Logic gates; Metals; on die capacitance; power integrity; Resistance; Silicon; silicon measurement
• DOI: 10.1109/ICEP-IAAC.2015.7111108

Transistor process technology continues to develop, the die size is shrinking approximately 20% to 35% with the process scaling. It is beneficial as smaller die can fit into several of small electronic devices for instance microprocessor watch and smart phone. In addition, the emerging market has intense needs on computing technology to build a smart and small device such as autonomous driving car. As a result, each of the IP has to shrink in order to fit into smaller form factor. Nevertheless, on die capacitance become one of the obstacles as it takes up approximately 30% of the die area. Since on die capacitance is a necessity to guarantee the circuit performance and however it also a showstopper from achieving smallest IP. Now, the question will be what is the balance point of meeting power noise performance yet meeting silicon area target? Thus, amount of on die capacitance become a key enabler for achieving smallest IP. In this paper, on die capacitance characterization was carried out. Several type of on die capacitance for instance power grid capacitance, metal capacitance as well as transistor device capacitance were simulated and characterized by different tool. The simulated result was then supported by correlation with lab measurement data.