Design of High Performance XOR and XNOR Logic Gates without MOS Devices

A design of high performance and area-efficient XOR and XNOR logic gates based on memristors is proposed, which consuming only 3 memristor cells and 3 clock cycles, 4 memristor cells and 4 clock cycles, respectively. The input of the gates is applied by voltage, and the output is presented as resist...

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Bibliographic Details
Published in2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC) pp. 1 - 2
Main Authors Lin, Qiujun, Cui, Xiaole, Xu, Xiaoyan
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2018
Subjects
Clocks
Delays
Equivalent circuits
Integrated circuit modeling
Logic gates
memristor
Memristors
Resistance
XNOR gate
XOR gate
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Summary:A design of high performance and area-efficient XOR and XNOR logic gates based on memristors is proposed, which consuming only 3 memristor cells and 3 clock cycles, 4 memristor cells and 4 clock cycles, respectively. The input of the gates is applied by voltage, and the output is presented as resistance value of the output cell. The proposed gates are MOS-less, and can be integrated into the 3D crossbar memristor array.
DOI:10.1109/EDSSC.2018.8487077