NBTI resistant SRAM design

• Published in: 2011 4th IEEE International Workshop on Advances in Sensors and Interfaces pp. 82 - 87
• Main Authors: Ahmed, F., Milor, L.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2011
• Subjects: Arrays; cache; Degradation; fault prediction; Monitoring; MOS devices; NBTI monitoring; Noise; Random access memory; reliability; SRAM cell; stability analysis; Stress
• ISBN: 9781457706233; 1457706237
• DOI: 10.1109/IWASI.2011.6004692

Increasing operating temperatures and electrical fields, combined with the scaling of dimensions, have contributed to faster device aging due to negative bias temperature instability (NBTI). This problem is further compounded in SRAM cells because SRAMs use devices that are among the smallest for a technology node. Since device degradation is a gradual process, it is proposed that if the threshold voltage increase in PMOS devices of SRAM cells can be monitored, failing cells in SRAMs can be detected and the SRAM can be operated without failures, given available memory redundancy. Using an experimentally verified NBTI model, we study the performances of conventional 6T SRAM cells, as a function of NBTI degradation, in the presence of process variations. An on-chip monitoring scheme is presented that can be embedded within conventional SRAM designs without affecting normal device operation. It identifies cells susceptible to read and write failures in the near future, enabling the prediction of cell failure before its occurrence in order to trigger reconfiguration.