FPGA-accelerated simulation of a hybrid-ARQ system using high level synthesis

• Published in: 2016 IEEE 37th Sarnoff Symposium pp. 19 - 21
• Main Authors: Mhaske, Swapnil, Hojin Kee, Tai Ly, Spasojevic, Predrag
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2016
• Subjects: Decoding; Encoding; Forward error correction; HARQ; HLS; Intellectual Property (IP); Peer-to-peer computing; QC-LDPC; Receivers; Throughput; Wireless communication
• DOI: 10.1109/SARNOF.2016.7846753

Physical layer processing for 5G wireless is expected to operate at a very high-throughput with very low latency. Developing a channel coding system based on Hybrid Automatic Repeat reQuest (HARQ) for evolving requirements necessitates extensive experimentation involving undesirably long development cycles. We demonstrate the use of a High-level Synthesis (HLS) compiler in LabVIEW Communications to prototype a real world HARQ system using Low-Density Parity-Check (LDPC) codes, however, without the expertise of an Hardware Description Language (HDL) designer. This implementation consumed 54% of the resources on our FPGA and allowed us to measure error-rate performance of the system over large, realistic data sets using accelerated, in-hardware simulation with a system throughput that is 4× greater than the CPU-based implementation. Furthermore, use of the HLS methodology significantly reduced time to explore the HARQ system parameter space and optimize in terms of error-rate performance and resource utilization.