A 3.0-5.0 GHz high linearity and low power CMOS up-conversion mixer for UWB applications

• Published in: 2010 IEEE International Conference of Electron Devices and Solid-State Circuits pp. 1 - 4
• Main Authors: Murad, S A Z, Pokharel, R K, Kanaya, H, Yoshida, K
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2010
• Subjects: Artificial neural networks; Capacitors; CMOS integrated circuits; conversion gain; high linearity; Layout; low-power; mixer; Mixers; Radio frequency; Semiconductor device modeling; up-conversion

This paper presents a high linearity and low power up-conversion mixer at 3.0-5.0 GHz for UWB applications in TSMC 0.18-μm CMOS technology. The design based on Gilbert-cell active double-balanced mixer using a capacitor located in parallel with the intrinsic gate-source capacitor of a transconductan...