A 3.0-5.0 GHz high linearity and low power CMOS up-conversion mixer for UWB applications

• Published in: 2010 IEEE International Conference of Electron Devices and Solid-State Circuits pp. 1 - 4
• Main Authors: Murad, S A Z, Pokharel, R K, Kanaya, H, Yoshida, K
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2010
• Subjects: Artificial neural networks; Capacitors; CMOS integrated circuits; conversion gain; high linearity; Layout; low-power; mixer; Mixers; Radio frequency; Semiconductor device modeling; up-conversion
• DOI: 10.1109/EDSSC.2010.5713741
• ISBN: 9781424499977; 1424499976

This paper presents a high linearity and low power up-conversion mixer at 3.0-5.0 GHz for UWB applications in TSMC 0.18-μm CMOS technology. The design based on Gilbert-cell active double-balanced mixer using a capacitor located in parallel with the intrinsic gate-source capacitor of a transconductance stage for high linearity. The source degeneration inductors helps to improve linearity and IF input matching. The current injection is employed to increase gain and obtained low power. The up-conversion mixer converts an input of 100 MHz intermediate frequency (IF) signal to an output of 3.0-5.0 GHz radio frequency (RF) signal. The post-layout simulation results indicated that the proposed mixer achieves a higher input third order intercept point (IIP3) of 13.5-dBm, convention gain of 2.3-dB and low power of 7.1-mW at 1.2-V power supply.