Sequential circuits test generation using GTL

The algorithm, which avoids drawbacks of conventional approaches, has been presented for not resetable lines using GTL(Global Temporal Logic). This model checking algorithm are subject to constant improvement so that the size of manageable circuits will future increased. In this paper, based on the...

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Bibliographic Details
Published in2011 International Conference on Electric Information and Control Engineering pp. 726 - 728
Main Authors He Xinhua, Zhao Yingkun
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2011
Subjects
Circuit faults
Digital circuits
Drawback
Force
Formal Logic
Global temporal Logic
Integrated circuit modeling
Logic gates
Sequential circuits
Test generation
Testing
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ISBN1424480361
9781424480364
DOI10.1109/ICEICE.2011.5777524

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Summary:The algorithm, which avoids drawbacks of conventional approaches, has been presented for not resetable lines using GTL(Global Temporal Logic). This model checking algorithm are subject to constant improvement so that the size of manageable circuits will future increased. In this paper, based on the global temporal logic that defined by forward and reverse operator, a common formal framework for test generation is presented. In addition, heuristic for accelerating the testing process and implementation are given.
ISBN:1424480361
9781424480364
DOI:10.1109/ICEICE.2011.5777524