Unique Challenges and Solutions in CMOS Compatible NVM

CMOS compatible NVM is finding increasing applications that range from a few bits in analog trim applications to kilobits for data or code. CMOS compatibility comes with unique retention and endurance challenges. The floating gate is in direct contact with backend dielectric, which degrades high tem...

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Bibliographic Details
Published in2006 7th Annual Non-Volatile Memory Technology Symposium pp. 52 - 54
Main Authors Jiankang Bu, Belcher, W., Parker, C., Prosack, H.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2006
Subjects
CMOS compatible
CMOS process
CMOS technology
Costs
Dielectrics
Doping profiles
Drain Avalanche Hot Carrier
endurance
Hot carriers
MOSFETs
Nonvolatile memory
NVM
oxynitride
System-on-a-chip
Temperature
Trap-Asssited-Tunneling
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Summary:CMOS compatible NVM is finding increasing applications that range from a few bits in analog trim applications to kilobits for data or code. CMOS compatibility comes with unique retention and endurance challenges. The floating gate is in direct contact with backend dielectric, which degrades high temperature data retention performance. Drain and well doping profile are not optimized to favor hot carrier generation and injection. Endurance is poor due to serious oxide damage. Mechanisms and preferred solutions are described. Experiment results match theoretical analysis.
ISBN:9780780397385
078039738X
DOI:10.1109/NVMT.2006.378876