A Neuromorphic Computing System for Bitwise Neural Networks Based on ReRAM Synaptic Array
Recent advances in neuromorphic computing system have shown resistive random-access memory (ReRAM) can be used to efficiently implement compact parallel computing arrays, which are inherently suitable for neural networks that require large amounts of matrix-vector multiplications (MVMs). In this wor...
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Published in | 2018 IEEE Biomedical Circuits and Systems Conference (BioCAS) pp. 1 - 4 |
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Main Authors | , , , , , , , , , , , |
Format | Conference Proceeding |
Language | English |
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01.10.2018
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Abstract | Recent advances in neuromorphic computing system have shown resistive random-access memory (ReRAM) can be used to efficiently implement compact parallel computing arrays, which are inherently suitable for neural networks that require large amounts of matrix-vector multiplications (MVMs). In this work, we proposed a neuromorphic computing system based on ReRAM synaptic array to implement bitwise neural networks. The system contains a ReRAM synaptic array for parallel computation of bitwise MVMs, and a field-programmable gate array for data buffering and processing. To deploy the network on the system, a customized training scheme was required to adapt the trained network to the characteristic of ReRAM synaptic array with bitwise weights and inputs. We also managed the resolution of partial sum to reduce the bit width requirement of sense amplifier, thereby reducing power consumption. The measurement results show that the ReRAM synaptic array consumed only 0.27mW at 1V supply by using 1-bit sense amplifier while the system still maintained 97.52% accuracy on MNIST dataset. |
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AbstractList | Recent advances in neuromorphic computing system have shown resistive random-access memory (ReRAM) can be used to efficiently implement compact parallel computing arrays, which are inherently suitable for neural networks that require large amounts of matrix-vector multiplications (MVMs). In this work, we proposed a neuromorphic computing system based on ReRAM synaptic array to implement bitwise neural networks. The system contains a ReRAM synaptic array for parallel computation of bitwise MVMs, and a field-programmable gate array for data buffering and processing. To deploy the network on the system, a customized training scheme was required to adapt the trained network to the characteristic of ReRAM synaptic array with bitwise weights and inputs. We also managed the resolution of partial sum to reduce the bit width requirement of sense amplifier, thereby reducing power consumption. The measurement results show that the ReRAM synaptic array consumed only 0.27mW at 1V supply by using 1-bit sense amplifier while the system still maintained 97.52% accuracy on MNIST dataset. |
Author | Li, Pin-Yi Tang, Kea-Tiong Wei, Wei-Chen Chang, Meng-Fan Liu, Je-Syu Huang, Jian-Hao Hsieh, Chih-Cheng Chen, Wei-Hao Hsu, Tzu- Hsiang Liu, Ren-Shuo Yang, Cheng-Han Lin, Wei-Yu |
Author_xml | – sequence: 1 givenname: Pin-Yi surname: Li fullname: Li, Pin-Yi organization: Department of Electrical Engineering, National Tsing Hua University, Hsinchu, 30013, Taiwan – sequence: 2 givenname: Ren-Shuo surname: Liu fullname: Liu, Ren-Shuo organization: Department of Electrical Engineering, National Tsing Hua University, Hsinchu, 30013, Taiwan – sequence: 3 givenname: Meng-Fan surname: Chang fullname: Chang, Meng-Fan organization: Department of Electrical Engineering, National Tsing Hua University, Hsinchu, 30013, Taiwan – sequence: 4 givenname: Kea-Tiong surname: Tang fullname: Tang, Kea-Tiong email: kttang@mx.nthu.edu.tw organization: Department of Electrical Engineering, National Tsing Hua University, Hsinchu, 30013, Taiwan – sequence: 5 givenname: Cheng-Han surname: Yang fullname: Yang, Cheng-Han organization: Department of Electrical Engineering, National Tsing Hua University, Hsinchu, 30013, Taiwan – sequence: 6 givenname: Wei-Hao surname: Chen fullname: Chen, Wei-Hao organization: Department of Electrical Engineering, National Tsing Hua University, Hsinchu, 30013, Taiwan – sequence: 7 givenname: Jian-Hao surname: Huang fullname: Huang, Jian-Hao organization: Department of Electrical Engineering, National Tsing Hua University, Hsinchu, 30013, Taiwan – sequence: 8 givenname: Wei-Chen surname: Wei fullname: Wei, Wei-Chen organization: Department of Electrical Engineering, National Tsing Hua University, Hsinchu, 30013, Taiwan – sequence: 9 givenname: Je-Syu surname: Liu fullname: Liu, Je-Syu organization: Department of Electrical Engineering, National Tsing Hua University, Hsinchu, 30013, Taiwan – sequence: 10 givenname: Wei-Yu surname: Lin fullname: Lin, Wei-Yu organization: Department of Electrical Engineering, National Tsing Hua University, Hsinchu, 30013, Taiwan – sequence: 11 givenname: Tzu- Hsiang surname: Hsu fullname: Hsu, Tzu- Hsiang organization: Department of Electrical Engineering, National Tsing Hua University, Hsinchu, 30013, Taiwan – sequence: 12 givenname: Chih-Cheng surname: Hsieh fullname: Hsieh, Chih-Cheng organization: Department of Electrical Engineering, National Tsing Hua University, Hsinchu, 30013, Taiwan |
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Snippet | Recent advances in neuromorphic computing system have shown resistive random-access memory (ReRAM) can be used to efficiently implement compact parallel... |
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SubjectTerms | Arrays bitwise neural network Computational modeling customized training scheme Field programmable gate arrays Neural networks neuromorphic computing system Neuromorphics Neurons ReRAM synaptic array Training |
Title | A Neuromorphic Computing System for Bitwise Neural Networks Based on ReRAM Synaptic Array |
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