Multithreaded pipeline synthesis for data-parallel kernels

• Published in: 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) pp. 718 - 725
• Main Authors: Mingxing Tan, Bin Liu, Dai, Steve, Zhiru Zhang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.11.2014
• Subjects: Context; Instruction sets; Kernel; Pipeline processing; Schedules; Switches; Throughput
• DOI: 10.1109/ICCAD.2014.7001431
• ISSN: 1092-3152

Pipelining is an important technique in high-level synthesis, which overlaps the execution of successive loop iterations or threads to achieve high throughput for loop/function kernels. Since existing pipelining techniques typically enforce in-order thread execution, a variable-latency operation in one thread would block all subsequent threads, resulting in considerable performance degradation. In this paper, we propose a multithreaded pipelining approach that enables context switching to allow out-of-order thread execution for data-parallel kernels. To ensure that the synthesized pipeline is complexity effective, we further propose efficient scheduling algorithms for minimizing the hardware overhead associated with context management. Experimental results show that our proposed techniques can significantly improve the effective pipeline throughput over conventional approaches while conserving hardware resources.