A pipelined simulation approach for logic emulation using multi-FPGA platforms

• Published in: 2009 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1141 - 1144
• Main Authors: Baviskar, D., Patkar, S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2009
• Subjects: Circuit simulation; Clocks; Costs; Emulation; Field programmable gate arrays; Logic; Pipeline processing; Scheduling; Throughput; Wires

Emulation of a large system on a multi-FPGA platform not only involves partitioning the system into multiple modules subject to given capacity and resource constraints, but also involves achieving higher throughput, lower cost of emulation and less communication overhead. Many good scheduling algori...