A pipelined simulation approach for logic emulation using multi-FPGA platforms

• Published in: 2009 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1141 - 1144
• Main Authors: Baviskar, D., Patkar, S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2009
• Subjects: Circuit simulation; Clocks; Costs; Emulation; Field programmable gate arrays; Logic; Pipeline processing; Scheduling; Throughput; Wires
• DOI: 10.1109/ISCAS.2009.5117962
• ISBN: 1424438276; 9781424438273
• ISSN: 0271-4302

Emulation of a large system on a multi-FPGA platform not only involves partitioning the system into multiple modules subject to given capacity and resource constraints, but also involves achieving higher throughput, lower cost of emulation and less communication overhead. Many good scheduling algorithms have been reported, however due to the lack of pipelining they fail to achieve high system throughput. An intelligent hardware scheduling approach is essential for obtaining high system throughput with possibly lower overheads. In this paper, we propose a scalable, high performance, low cost approach for simulation of multi-FPGA systems. We convert the unbalanced partitioned system into a balanced pipeline and maximize the throughput of the system. Our experiments on reference designs have shown a speed-up of up to 8.57times with a 10% hardware overhead over the conventional simulation approaches.