Further Studies on Zero-Aliasing Space Compression Based on Graph Theory

• Published in: 2007 IEEE Instrumentation & Measurement Technology Conference IMTC 2007 pp. 1 - 6
• Main Authors: Hossain, A., Das, S.R., Nayak, A.R., Petriu, E.M., Biswas, S., Sahinoglu, M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2007
• Subjects: Aliasing-free space compactor; Built-in self-test; Circuit faults; Circuit testing; Circuits and systems; cores-based system-on-Chip (SOC); Corporate acquisitions; Graph theory; Hardware; maximal compatibility classes (MCCs); maximal minimally strongly connected (MMSC) subgraphs; nonminimally strongly connected (NMSC) pairs of vertices; Sequential analysis; System-on-a-chip; Very large scale integration

The design of space-efficient support hardware for built-in self-testing (BIST) is of great significance in the realization of present day very large scale integration (VLSI) circuits and systems, particularly in the context of design paradigm shift from system-onboard to system-on-chip (SOC). This...