Nop compression scheme for high speed DSPs based on VLIW architecture

VLIW (Very Long Instruction Word) is one of the most popular architectures in embedded systems because it has features of low power consumption and low hardware cost. Due to the nature of VLIW architecture such as bundled instructions and large register files, VLIW processors are running with large...

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Bibliographic Details
Published in2014 IEEE International Conference on Consumer Electronics (ICCE) pp. 304 - 305
Main Authors Taisong Jin, Minwook Ahn, Donghoon Yoo, Dongkwan Suh, Yoonseo Choi, Do-Hyung Kim, Shihwa Lee
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.01.2014
Subjects
Acceleration
Clocks
Consumer electronics
Digital signal processing
Hardware
Program processors
VLIW
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Summary:VLIW (Very Long Instruction Word) is one of the most popular architectures in embedded systems because it has features of low power consumption and low hardware cost. Due to the nature of VLIW architecture such as bundled instructions and large register files, VLIW processors are running with large size of instruction codes in relatively low clock frequency. However compact instruction size and high clock frequency are the most important requirements of modern embedded consumer electronics. In this paper we propose a novel instruction compression scheme to solve the addressed problem. The experiment shows that the proposed scheme can reduce instruction size by 23% and improve clock frequency by 25% in average comparing with conventional compression schemes.
ISSN:2158-3994
2158-4001
DOI:10.1109/ICCE.2014.6776016