Route-on-Fly: A single cycle router

• Published in: 2017 4th International Conference on Signal Processing and Integrated Networks (SPIN) pp. 109 - 114
• Main Authors: Ved, Sneha N., Bhange, Ankit, Arya, Aparna, Mekie, Joycee
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2017
• Subjects: Delays; Multicore processing; Multiplexing; Ports (Computers); Routing; Switches
• DOI: 10.1109/SPIN.2017.8049926

Network-on-Chip (NoC) architecture provides a platform for inter-core communication in a multicore system. In this work we propose a single cycle minimally buffered Route-on-Fly (RoF) router that uses the link traversal time of the data packet to perform route calculations. We also propose a 2 cycle variant of the Route-on-Fly (RoF) router in this paper. 4 × 4 NoC meshes built using proposed architectures and the baseline router have been synthesized on 28nm Xilinx Kintex7 KC705 FPGA to assess for implementability. We show that the proposed single cycle minimally buffered Route-on-Fly router based NoC occupies 94% less memory cells and 30% less router latency than the baseline router synthesized. A detailed performance analysis shows that even in the best case of single link contention, the proposed Route-on-Fly NoC outperforms the bufferless NoC by about 20% and the baseline NoC by about 75%.