FPGA implementation of a lossy compression algorithm for hyperspectral images with a high-level synthesis tool

• Published in: 2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2013) pp. 107 - 114
• Main Authors: Santos, Lucana, Lopez, Jose Fco, Sarmiento, Roberto, Vitulli, Raffaele
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2013
• Subjects: Algorithm design and analysis; Field programmable gate arrays; Hardware; Hyperspectral imaging; Image coding; Prediction algorithms
• DOI: 10.1109/AHS.2013.6604233

In this paper, we present an FPGA implementation of a novel adaptive and predictive algorithm for lossy hyperspectral image compression. This algorithm was specifically designed for on-board compression, where FPGAs are the most attractive and popular option, featuring low power and high-performance. However, the traditional RTL design flow is rather time-consuming. High-level synthesis (HLS) tools, like the well-known CatapultC, can help to shorten these times. Utilizing CatapultC, we obtain an FPGA implementation of the lossy compression algorithm directly from a source code written in C language with a double motivation: demonstrating how well the lossy compression algorithm would perform on an FPGA in terms of throughput and area; and at the same time showing how HLS is applied, in terms of source code preparation and CatapultC settings, to obtain an efficient hardware implementation in a relatively short time. The P&R on a Virtex 5 5VFX130 displays effective performance terms of area (maximum device utilization at 14%) and frequency (80 MHz). A comparison with a previous FPGA implementation of a lossless to near-lossless algorithm is also provided. Results on a Virtex 4 4VLX200 show less memory requirements and higher frequency for the LCE algorithm.