Performance improvement of QPSK modem implemented in FPGA

• Published in: 2015 International Conference on Smart Sensors and Systems (IC-SSS) pp. 1 - 6
• Main Authors: Umesharaddy, Sujatha, B. K.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2015
• Subjects: Binary phase shift keying; Booth Algorithm; Field programmable gate arrays; FPGA; Hardware design languages; Modulation; QPSK; Read only memory; Verilog
• DOI: 10.1109/SMARTSENS.2015.7873621

This paper proposes a Quadrature Phase Shift Keying (QPSK) using two different methods. QPSK is one of the forms of Phase Shift Keying (PSK) modulation scheme. Generally a conventional QPSK modulator with Direct Digital Synthesizer (DDS) and arithmetic multiplier separates base band signal into I and Q phase which consumes low throughput with complexity in hardware implementation. Hence to generate high throughput QPSK modulator, the first proposal uses an up and down accumulator for carrier generator instead of DDS and arithmetic multiplier is modified as BOOTH multiplier. The second proposed method will produce the QPSK signal, which is based on stored QPSK phase data in ROM, which eliminates completely the DDS and multiplier blocks of the modulator.