TSV technology and challenges for 3D stacked DRAM

A successful integration of Via-middle TSV process in DRAM technology with major process issues is introduced. Fast TSV open/short detection and how to trade-off in choice repair scheme is discussed. Process development for TSV volume shrink required to reduce dynamic power for driving TSV. Fast Cu...

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Bibliographic Details
Published in2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers pp. 1 - 2
Main Authors Chang Yeol Lee, Sungchul Kim, Hongshin Jun, Kyung Whan Kim, Sung Joo Hong
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2014
Subjects
Maintenance engineering
Metals
Process control
Random access memory
Stacking
Three-dimensional displays
Through-silicon vias
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Summary:A successful integration of Via-middle TSV process in DRAM technology with major process issues is introduced. Fast TSV open/short detection and how to trade-off in choice repair scheme is discussed. Process development for TSV volume shrink required to reduce dynamic power for driving TSV. Fast Cu leak monitor method is essential to sustaining good quality and Fab process control.
ISBN:9781479933310
1479933317
ISSN:0743-1562
DOI:10.1109/VLSIT.2014.6894397