High speed multiplier implementation based on Vedic Mathematics

• Published in: 2015 International Conference on Smart Sensors and Systems (IC-SSS) pp. 1 - 5
• Main Authors: Meghana, V., Sandhya, S., Aparna, R., Gururaj, C.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2015
• Subjects: Adders; Array Multiplier; Delays; Digital signal processing; Field programmable gate arrays; FPGA; Mathematics; Propagation Delay; Ripple Carry Adder; Table lookup; Vedic Multiplier; VHDL
• DOI: 10.1109/SMARTSENS.2015.7873593

The proposed multiplier pertaining to concepts of Vedic Mathematics was designed to reduce propagation delay, design complexity as well as to optimize power consumption in comparison to conventional multipliers. A multiplier is a key element in DSP systems, serving as a building block of most computational digital systems, therefore, speed and power consumption are two important parameters of design. The Vedic Multiplier computed the partial products in a simultaneous manner and the carry was propagated using ripple carry adders. The higher bit-multipliers were designed using lower-bit multipliers, giving the multiplier a modular structure, thereby reducing the design complexity. The designed 8×8 Vedic Multiplier was coded in VHDL. The results were simulated using the Xilinx Tool and synthesized using System Generator tool on the FPGA board Spartan 1×45-324. Upon simulation of the results, the Vedic Multiplier was found to restrict the delay, compared to the Array and Booth Multipliers.