Device-level PBTI-induced timing jitter increase in circuit-speed random logic operation - Lu, J. W.; Vaz, C.; Campbell, J. P.; Ryan, J. T.; Cheung, K. P.; Jiao, G. F.; Bersuker, G.; Young, C. D. (Digest of technical papers - Symposium on VLSI Technology, 2014)
Keywords: Degradation; Logic gates; Stress; Stress measurement; Time measurement; Timing jitter