An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS

We present a robust, all-digital True Random Number Generator (TRNG) architecture that efficiently combines low-quality physical random number generators (PRNGs) with integrated de-correlation and de-biasing. A 65-nm CMOS TRNG test chip demonstrates NIST test-suite compliance across 0.5-1.0 V supply...

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Bibliographic Details
Published in2018 IEEE Symposium on VLSI Circuits pp. 1 - 2
Main Authors Pamula, V. Rajesh, Xun Sun, Sung Kim, Ur Rahman, Fahim, Baosen Zhang, Sathe, Visvesh S.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2018
Subjects
Bit rate
Correlation
Entropy
Markov processes
NIST
Radio frequency
Very large scale integration
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DOI10.1109/VLSIC.2018.8502375

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Summary:We present a robust, all-digital True Random Number Generator (TRNG) architecture that efficiently combines low-quality physical random number generators (PRNGs) with integrated de-correlation and de-biasing. A 65-nm CMOS TRNG test chip demonstrates NIST test-suite compliance across 0.5-1.0 V supply voltage (V dd ) and -20 - 100 °C, even with significant PRNG entropy (H) degradation. The measured 2.58 pJ/bit is the lowest among all-digital NIST-compliant TRNGs. In terms of energy, area and performance metrics, this digital implementation is especially suited for advanced CMOS process nodes.
DOI:10.1109/VLSIC.2018.8502375