APA (7th ed.) Citation

Pamula, V. R., Sun, X., Kim, S., Ur Rahman, F., Zhang, B., & Sathe, V. S. (2018, June). An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS. 2018 IEEE Symposium on VLSI Circuits, 1-2. https://doi.org/10.1109/VLSIC.2018.8502375

Chicago Style (17th ed.) Citation

Pamula, V. Rajesh, Xun Sun, Sung Kim, Fahim Ur Rahman, Baosen Zhang, and Visvesh S. Sathe. "An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS." 2018 IEEE Symposium on VLSI Circuits Jun. 2018: 1-2. https://doi.org/10.1109/VLSIC.2018.8502375.

MLA (9th ed.) Citation

Pamula, V. Rajesh, et al. "An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS." 2018 IEEE Symposium on VLSI Circuits, Jun. 2018, pp. 1-2, https://doi.org/10.1109/VLSIC.2018.8502375.