Very Wide Register: An Asymmetric Register File Organization for Low Power Embedded Processors

• Published in: 2007 Design, Automation & Test in Europe Conference & Exhibition pp. 1 - 6
• Main Authors: Raghavan, P., Lambrechts, A., Jayapala, M., Catthoor, F., Verkest, D., Corporaal, H.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.04.2007
• Subjects: Computer architecture; Costs; Digital signal processing; Embedded system; Energy efficiency; Kernel; Parallel processing; Radio frequency; Registers; Software radio
• DOI: 10.1109/DATE.2007.364435
• ISBN: 3981080122; 9783981080124
• ISSN: 1530-1591

In current embedded systems processors, multi-ported register files are one of the most power hungry parts of the processor, even when they are clustered. This paper presents a novel register file architecture, which has single ported cells and asymmetric interfaces to the memory and to the datapath. Several realistic kernels from the TI DSP benchmark and from software defined radio (SDR) are mapped on the architecture. A complete physical design of the architecture is done in TSMC 90nm technology. The novel architecture presented is shown to obtain energy gains of up to 10times with respect to conventional multi-ported register file over the different benchmarks