Current carry capacity characterization for high performance system on chip packages

• Published in: 2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) pp. 1 - 3
• Main Authors: Ng Hui Ying, Wong Wui Weng
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2015
• Subjects: Current distribution; Electronics packaging; Heating; Pins; Power demand; System-on-chip; Temperature distribution
• DOI: 10.1109/EPTC.2015.7412285

System on Chip (SoC) technology is rapidly evolved across high power workstations to low power tablets. As complex SoC further integrates several hardware functionalities, the system-level on-chip architecture is emerging as a significant source of power consumption. Improving current carry capacity (CCC) of existing packages can be one of factors to enhance power consumption with minimum cost. To deal with thermal effects of joule heating in a typical high pin count organic substrate of today SOC, a test vehicle was energized with various current levels and the correspondent temperature rise was measured. This paper introduces an effective current carry capacity characterization method to investigate the ability of pins to support higher current levels. It can be achieved by setting the test environment resembled to application conditions and to challenge operating limit which defined by a conservative approach. Up to 20% improvement in higher current carrying capacity was observed, which could ultimately translate into performance and power gain in today SOC with a complex package.