Process and characterization of Strained Silicon MOSFET incorporating Dielectric Pocket (SDP-MOSFET)

• Published in: 2011 IEEE Regional Symposium on Micro and Nano Electronics pp. 36 - 39
• Main Authors: Napiah, Z. A. F. M., Idris, M. I., Said, M. M., Hamid, A. M. A., Ali, N. A., Hamzah, R. A.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2011
• Subjects: Dielectrics; Doping; Logic gates; MOSFET circuits; Silicon; Silicon germanium; Strain
• DOI: 10.1109/RSM.2011.6088286
• ISBN: 1612848443; 9781612848440

In this paper, we propose a fabrication process of Strained Silicon MOSFET incorporating Dielectric Pocket (SDP-MOSFET). By employing TCAD tools, a systematic process simulation in realizing the SDP-MOSFET structure is done successfully. By using vertical and horizontal doping profiles, 120 nm gate length with 12 nm gate oxide of the device is observed respectively. The combination of a Silicon Germanium (SiGe) layer and incorporation of dielectric pocket (DP) shows an improved in suppression of short channel effects (SCE) and allows the threshold voltage and the performance of the devices to be optimized. A low leakage current (I OFF ), good drive current (I ON ), higher mobility and lower power consumption are obtained in SDP-MOSFET. Consequently, the threshold voltage (V T ) is decreased accordingly in SDP-MOSFET devices and shows a better control of V T roll-off.