Layered T comparator design using quantum-dot cellular automata - Roy, Soudip Sinha; Mukherjee, Chiradeep; Panda, Saradindu; Mukhopadhyay, Asish Kumar; Maji, Bansibadan (2017 Devices for Integrated Circuit (DevIC), 2017)
Keywords: 1-bit Comparator; Automata; Fault tolerance; Fault tolerant systems; Integrated circuits; Layered T Gate; Layout; Logic gates; Quantum dots; Quantum-dot Cellular Automata; universal gates