Clock Tree Synthesis and optimization in BES1300 IC Smart Card

• Published in: 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) pp. 846 - 848
• Main Authors: Fei Xie, Peiyuan Wan
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2016
• Subjects: Clocks; Integrated circuits; Manuals

This paper provides several methods by using Synopsys IC Compiler (ICC) to optimize Clock Tree Synthesis (CTS), reasonable floorplan, parameter constraint, manual specification, Engineering Change Order (ECO) included. An IC smartcard named BES1300 using 0.18μm EFLASH 2P4M technology is applied to v...