An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensor

We have developed a fully logic-MOS-transistor designed on-chip digitally controlled LDO in 40 nm CMOS. The proposed TDC-based voltage sensor used as an ADC can reduce the offset error almost to zero. The area of this LDO with no analog circuits is only 0.057 mm 2 . To suppress the AC voltage drop d...

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Bibliographic Details
Published in2012 IEEE International SOC Conference pp. 11 - 14
Main Authors Otsuga, K., Onouchi, M., Igarashi, Y., Ikeya, T., Morita, S., Ishibashi, K., Yanagisawa, K.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2012
Subjects
Clocks
Noise
System-on-a-chip
Transient analysis
Transient response
Voltage control
Voltage measurement
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Summary:We have developed a fully logic-MOS-transistor designed on-chip digitally controlled LDO in 40 nm CMOS. The proposed TDC-based voltage sensor used as an ADC can reduce the offset error almost to zero. The area of this LDO with no analog circuits is only 0.057 mm 2 . To suppress the AC voltage drop due to large load transient (LLT), we developed a LLT control method using dynamic sampling clock frequency scaling scheme. The measurement results show that the AC voltage drop can be suppressed to 50%. The peak efficiency is 99% at 250 mA.
ISBN:9781467312943
1467312940
ISSN:2164-1676
2164-1706
DOI:10.1109/SOCC.2012.6398369