Transistor optimization for leakage power management in a 65 nm CMOS technology for wireless and mobile applications

• Published in: Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004 pp. 14 - 15
• Main Authors: Zhao, S., Chatterjee, A., Tang, S., Yoon, J., Crank, S., Bu, H., Houston, T., Sadra, K., Jain, A., Wang, Y., Redwine, D., Chen, Y., Siddiqui, S., Zhang, G., Laaksonen, T., Hall, C., Chang, S., Olsen, L., Riley, T., Meek, C., Hossain, I., Rosal, J., Tsao, A., Wu, J., Scott, D.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2004
• Subjects: Capacitive sensors; Circuits; CMOS technology; Design engineering; Energy management; Logic; Optimization methods; Random access memory; Technology management; Transistors
• ISBN: 0780382897; 9780780382893
• DOI: 10.1109/VLSIT.2004.1345365

This paper presents a transistor optimization methodology tailored for wireless, digital consumer, and mobile applications that employ power management circuit techniques. This methodology is applied to a 65nm technology that supports a high-density (<0.5 um/sup 2/) embedded 6T SRAM cell. High performance logic (I/sub dn//I/sub dp/ = 550/300uA/um at L/sub poly/ = 39nm) and low leakage are achieved simultaneously by employing a data retention mode for the SRAM (I/sub leakage/ /spl sim/2pA/bit). Retention mode bias conditions and selective gate sizing in the SRAM reduces leakage by /spl sim/300X. Advanced transistor design including SSR channel, strain engineering, drain-extension (HDD) offset spacer, and HDD and halo profile optimization is used to achieve at least an additional 4/spl times/ reduction in leakage.