Yield Model for Planning and Controlling the Manufacture of VLSI Memory Chips

The subject of this paper is a yield model that has been used for optimizing chip productivity, planning, manufacturing, learning, and controlling the manufacture of VLSI memory chips. Examples of the use of this model and results are described.

Saved in:
Bibliographic Details
Published in1985 Symposium on VLSI Technology : Kobe, Japan, May 14-16, 1985 pp. 6 - 7
Main Author Stapper, Charles H.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.1985
Subjects
Circuit faults
Contact resistance
Productivity
Pulp manufacturing
Random access memory
Semiconductor device modeling
Statistics
Technology planning
Very large scale integration
Virtual manufacturing
Online AccessGet full text

Cover

More Information
Summary:The subject of this paper is a yield model that has been used for optimizing chip productivity, planning, manufacturing, learning, and controlling the manufacture of VLSI memory chips. Examples of the use of this model and results are described.
ISBN:9784930813091
4930813093