Reconfigurable synchronized dataflow processor

This paper describes the design and implementation of a reconfigurable synchronized dataflow processor (RSDP). The RSDP can configure its hardware to directly represent dataflow graphs (DFGs) of applications. Data are processed while they flow along application-specific datapaths in the RSDP. We hav...

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Bibliographic Details
Published inProceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106) pp. 27 - 28
Main Authors Sasaki, H., Maruyama, H., Kobayashi, H., Nakamura, T., Tsukioka, H., Shoji, N.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2000
Subjects
Application software
Computational modeling
Delay
Filters
Frequency synchronization
Functional programming
Hardware
Integrated circuit interconnections
Read-write memory
Registers
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Summary:This paper describes the design and implementation of a reconfigurable synchronized dataflow processor (RSDP). The RSDP can configure its hardware to directly represent dataflow graphs (DFGs) of applications. Data are processed while they flow along application-specific datapaths in the RSDP. We have designed three DFGs for benchmarking and evaluated their performance on an RSDP board. The results show that the RSDP running at relatively lower frequency can achieve a competitive performance with a general-purpose processor.
ISBN:9780780359734
0780359739
DOI:10.1109/ASPDAC.2000.835062