Ending the Tyranny of the Clock: SAT-Based Clock Number Assignment for Field-Coupled Nanotechnologies

• Published in: 2024 IEEE 24th International Conference on Nanotechnology (NANO) pp. 68 - 73
• Main Authors: Walter, Marcel, Drewniok, Jan, Wille, Robert
• Format: Conference Proceeding
• Language: English
• Published: IEEE 08.07.2024
• Subjects: Complexity theory; Design automation; Information processing; Layout; Runtime; Scalability; Simulation
• ISSN: 1944-9380
• DOI: 10.1109/NANO61778.2024.10628908

This paper presents an algorithm for clock num-ber assignment in the physical design process of Field-coupled Nanocomputing (FCN), a set of promising beyond-CMOS tech-nologies that manipulate physical fields instead of electrical currents for computation and information transmission. Clocking has traditionally been a significant obstacle to the scalability of FCN physical design algorithms, requiring pre-defined clocking schemes that limit the quality of circuit layouts and add complexity to the design process. Our proposed method utilizes Boolean Satisfiability (SAT) solving to facilitate the assignment of clock numbers without the need for predefined clocking, while ensuring compliance with technological constraints on information flow and synchronization. Via an experimental evaluation, we confirm the proposed al-gorithm's versatility to reconstruct clock assignments for diverse clocking schemes in reasonable runtime, and its scalability up to layouts with a half-million tiles. Thereby, we are potentially paving the way for a new era of physical design algorithms that are not constrained by the limitations of predefined clocking schemes. This research suggests a move towards physical design strategies adapted from conventional design automation, potentially mitigating one of the major challenges to FCN's further development.