A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur

• Published in: 2022 IEEE International Solid- State Circuits Conference (ISSCC) Vol. 65; pp. 1 - 3
• Main Authors: Tsai, Tsung-Hsien, Sheen, Ruey-Bin, Hsu, Sheng-Yun, Chang, Ya-Tin, Chang, Chih-Hsien, Staszewski, Robert Bogdan
• Format: Conference Proceeding
• Language: English
• Published: IEEE 20.02.2022
• Subjects: 5G mobile communication; Bandwidth; Conferences; Frequency conversion; Jitter; Phase noise
• DOI: 10.1109/ISSCC42614.2022.9731676

Many PLLs, including those used for mm-wave 5G communications, require deep-sub-picosecond integrated phase jitter [1]. Their in-band phase noise (PN) can be adversely affected by flicker noise and a large feedback frequency-division ratio, N. Cascaded PLLs are a recent trend in addressing this problem [2]-[4]. They are composed of two stages: the 1 st stage (PLL #1) receives an external frequency reference F REF to generate a filtered reference of several GHz feeding into the 2 nd stage (PLL #2) that features a lower division ratio and a wide bandwidth for better overall jitter performance. Although the cascaded PLL can chose from various combinations of oscillators, e.g., LC-tank and ring-oscillator (RO), the PLL #2 using an RO can benefit from a small size, easy integration, wide frequency-tuning range (FTR), and multiphase clock outputs (e.g., for directly supporting multibeam antenna arrays). Normally, the RO-PLL cannot achieve the same jitter performance as an LC-PLL, but here a low value of N in the wide-bandwidth integer-N configuration of PLL #2 makes this distinction less relevant.