Reduction of leakage current and power in full subtractor using MTCMOS technique

• Published in: 2013 International Conference on Computer Communication and Informatics pp. 1 - 4
• Main Authors: Gautam, M., Akashe, S.
• Format: Conference Proceeding Journal Article
• Language: English
• Published: IEEE 01.01.2013
• Subjects: cmos circuit; CMOS integrated circuits; CMOS technology; Computer simulation; Design engineering; Electric power generation; full subtractor; Integrated circuits; Leakage current; Logic gates; low power design; MTCMOS; Nanostructure; Power dissipation; Transistors; Very large scale integration
• ISBN: 1467329061; 9781467329064
• DOI: 10.1109/ICCCI.2013.6466143

In this paper a full subtractor using MTCMOS technique design is proposed. Combinational logic has extensive applications in quantum computing, low power VLSI design and optical computing. Reducing power dissipation is one of the most principle subjects in VLSI design today. But Scaling causes sub threshold leakage currents to become a large component of total power dissipation. Low-power design techniques proposed to minimize the active leakage power in nanoscale CMOS very large scale integration (VLSI) systems. Using MTCMOS approach compare leakage current and leakage power of full subtractor in active mode. leakage current in conventional full subtractor is 228.7 fA and proposed full subtractor is 271.1 fA, reduction in current is 15.63%. simulation result is performed at 0.7 volt using cadence virtuoso tool in 45 nanometer technology.