APA (7th ed.) Citation

Zanotti, T., Puglisi, F. M., & Pavan, P. (2021, March). Low-Bit Precision Neural Network Architecture with High Immunity to Variability and Random Telegraph Noise based on Resistive Memories. IEEE International Reliability Physics Symposium proceedings, 1-6. https://doi.org/10.1109/IRPS46558.2021.9405103

Chicago Style (17th ed.) Citation

Zanotti, Tommaso, Francesco Maria Puglisi, and Paolo Pavan. "Low-Bit Precision Neural Network Architecture with High Immunity to Variability and Random Telegraph Noise Based on Resistive Memories." IEEE International Reliability Physics Symposium Proceedings Mar. 2021: 1-6. https://doi.org/10.1109/IRPS46558.2021.9405103.

MLA (9th ed.) Citation

Zanotti, Tommaso, et al. "Low-Bit Precision Neural Network Architecture with High Immunity to Variability and Random Telegraph Noise Based on Resistive Memories." IEEE International Reliability Physics Symposium Proceedings, Mar. 2021, pp. 1-6, https://doi.org/10.1109/IRPS46558.2021.9405103.