Adaptable Register File Organization for Vector Processors

• Published in: 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA) pp. 786 - 799
• Main Authors: Lazo, Cristobal Ramirez, Reggiani, Enrico, Morales, Carlos Rojas, Figueras Bague, Roger, Villa Vargas, Luis A., Ramirez Salinas, Marco A., Cortes, Mateo Valero, Sabri Unsal, Osman, Cristal, Adrian
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.04.2022
• Subjects: Computer architecture; data-level parallelism; Graphics processing units; Measurement; Microarchitecture; Power demand; Processor scheduling; Support vector machines; vector architectures; vector register file

Contemporary Vector Processors (VPs) are de-signed either for short vector lengths, e.g., Fujitsu A64FX with 512-bit ARM SVE vector support, or long vectors, e.g., NEC Aurora Tsubasa with 16Kbits Maximum Vector Length (MVL 1 ). Unfortunately, both approaches have drawbacks. On the one hand, short ve...